Assuming that your AO output signals are electrically compatible with the devices you're driving with PWM, it should be possible. You just have to think through your old math lessons on factors and multiples carefully. (The
1. All the AO channels will share the same update/sample clock. So you first need to find a sample rate that allows you to generate the desired frequencies. Bear in mind that at 50% duty cycle, you need to define samples at a minimum of 2x the listed freqs to create both the rising and falling edges.
2. So the minimum candidate freq is 2x 185 = 370 Hz. That's a cycle time (period) of 2.7027027.... msec. Here's our first little hitch. You can't produce an exact 370 Hz sample clock because the period is an infinitely repeating decimal. Let's see how close we get with a period of 2.70 msec -- ok, that'll be an update rate of 370.37 Hz which is only 0.1 % away from our target.
3. Next question. If we have a 2.70 msec update interval, can we properly define our 50 hz and 100 hz PWM signals? Well, following similar reasoning as above, they'll need an update rate that'll divide evenly into 5.00 msec. At a quick glance, it appears that we'd better pick a sample clock interval of 0.10 msec or 10 kHz. Then we can define integer #'s of samples to land on either 2.70 msec or 5.00 msec boundaries as needed. So, for the 185.185 Hz PWM signal, you'll make an alternating pattern of 27 low samples followed by 27 high samples. For the 100 Hz signal, the pattern will be 50 lows followed by 50 highs. For the 50 Hz signal, the pattern is 100 lows followed by 100 highs.
4. Next we need to determine a least multiple of all the PWM's period times. That'll let us define a single buffer which contains exact integer quantities of each PWM. So, least multiple of 54 samples and 200 samples is 5400 samples. With a total buffer size of 5400 samples, we'll fit exactly 100 cycles of the 185.185 Hz PWM (each cycle is 27 low and 27 high) and we'll fit exactly 27 cycles of the 50 Hz PWM(each cycle is 100 low and 100 high). Similarly, we'll get exactly 54 cycles of the 100 Hz PWM.
5. What I'd do (if you can spare another counter). I'd generate the 185 Hz with the other counter and only generate 50 and 100 Hz with AO. That'd save all the math above. All you'd need is a 4 sample repeating buffer for AO. The 100 Hz channel would go low,high,low,high while the 50 Hz channel would go low,low,high,high. Then set your AO output rate for 200 Hz. Done.
-Kevin P.